Lead Logic Design Engineer
Astera Labs · Bengaluru, Karnataka, India
6-10 YOE www.asteralabs.com . Lead Logic Design Engineer – UALink IP/Subsystem Experience 6–10 years Job Summary Lead RTL and microarchitecture development for UALink-based IP/subsystems, focusing on high-bandwidth, low-latency
This posting is pulled directly from Astera Labs's own Greenhouse page and applying happens on their site, not here. Posted 2026-09-23; Skip The Boards re-checks every company's board regularly and removes listings that disappear from the source.