Senior Design Verification Engineer
Astera Labs · San Jose, California, United States
2-5 YOE Electrical Engineering , Computer Engineering, or a related technical field. 2–5 years of experience in design verification for complex ASICs or SoCs. Hands-on experience with SystemVerilog
Python
This posting is pulled directly from Astera Labs's own Greenhouse page and applying happens on their site, not here. Posted 2026-10-08; Skip The Boards re-checks every company's board regularly and removes listings that disappear from the source.