Principal Advanced Packaging Engineer
Astera Labs · Taipei, Taiwan
8+ YOE Lead R&D for advanced packaging of optical chips, including 2.1D, 2.5D, and 3D integration.; Define and optimize wafer-level, panel-level, or die-level packaging process flows.; Drive EIC-to-PIC integration and broader…
This posting is pulled directly from Astera Labs's own Greenhouse page and applying happens on their site, not here. Posted 2026-09-23; Skip The Boards re-checks every company's board regularly and removes listings that disappear from the source.