Principal / Senior Principal Design Verification Engineer- CXL / PCIe / Ethernet
Astera Labs · San Jose, California, United States
Lead the verification strategy for complex IPs and SoC subsystems from architecture through silicon.; Define verification methodologies, reusable verification frameworks, and best practices across multiple programs…
Python
This posting is pulled directly from Astera Labs's own Greenhouse page and applying happens on their site, not here. Posted 2026-09-23; Skip The Boards re-checks every company's board regularly and removes listings that disappear from the source.