Staff/ Principal Chip Top Physical Design Engineer
Astera Labs · Tel Aviv-Yafo, Tel Aviv District, Israel
5+ YOE Execute SoC Top-level physical design and actively drive full-chip convergence; Perform Top-Level physical implementation, including floor-planning, Place & Route (P&R), Clock Tree Synthesis (CTS), Power/Clock…
This posting is pulled directly from Astera Labs's own Greenhouse page and applying happens on their site, not here. Posted 2026-08-25; Skip The Boards re-checks every company's board regularly and removes listings that disappear from the source.