Design Verification Engineer (Silicon Engineering)
SpaceX · Palo Alto, CA
1+ YOE Responsible for digital ASIC verification at block and system level; Write and review test plans, develop test harnesses and test sequences; Develop SystemVerilog testbench infrastructure (both UVM and non-UVM) for…
Python
This posting is pulled directly from SpaceX's own Greenhouse page and applying happens on their site, not here. Posted 2026-07-24; Skip The Boards re-checks every company's board regularly and removes listings that disappear from the source.