Design Verification Tech Lead- SerDes/PHY IP
Astera Labs · San Jose, California, United States
5+ YOE Verification Architecture & Strategy; Architect UVM-based verification environments for SerDes/PHY IP, including PMA, PCS, and PHY-MAC interface layers; Define verification plans, coverage models, and sign-off criteria…
Python
This posting is pulled directly from Astera Labs's own Greenhouse page and applying happens on their site, not here. Posted 2026-09-23; Skip The Boards re-checks every company's board regularly and removes listings that disappear from the source.