Tech Lead, Digital Design Engineer
Astera Labs · San Jose, California, United States
5-8 YOE Digital Architecture and RTL Design Define microarchitecture and implement synthesizable RTL for complex switch ASIC blocks.; Develop front-end design solutions for high-performance networking and server connectivity…
Python
This posting is pulled directly from Astera Labs's own Greenhouse page and applying happens on their site, not here. Posted 2026-09-30; Skip The Boards re-checks every company's board regularly and removes listings that disappear from the source.