Manager Design Verification
Astera Labs · Tel Aviv-Yafo, Tel Aviv District, Israel
5+ YOE RTL Design & Implementation Own RTL design for assigned blocks from microarchitecture through synthesis sign-off; Develop high-quality, synthesizable Verilog/SystemVerilog with strong attention to PPA; Drive design…
This posting is pulled directly from Astera Labs's own Greenhouse page and applying happens on their site, not here. Posted 2026-09-23; Skip The Boards re-checks every company's board regularly and removes listings that disappear from the source.