Principal Digital RTL Engineer
Astera Labs · San Jose, California, United States
8+ YOE Circuit Design & Architecture Architect, design, and optimize high-speed analog/mixed-signal circuits such as SerDes, PLLs/clocking, ADCs/DACs, LDOs, and bias/reference blocks; Define block-level specifications and…
This posting is pulled directly from Astera Labs's own Greenhouse page and applying happens on their site, not here. Posted 2026-08-25; Skip The Boards re-checks every company's board regularly and removes listings that disappear from the source.