RTL Design Engineer (Silicon Engineering)
SpaceX · Irvine, CA
1+ YOE Design ASICs and/or FPGAs for Starlink projects, implementing IP for complex SoCs and participate in integration tasks using Verilog/SystemVerilog; Participate in the full ASIC/FPGA design lifecycle for Starlink…
Python
This posting is pulled directly from SpaceX's own Greenhouse page and applying happens on their site, not here. Posted 2026-07-24; Skip The Boards re-checks every company's board regularly and removes listings that disappear from the source.