Principal Analog Mixed-Signal Design Engineer
Astera Labs · Ho Chi Minh City, Vietnam
8+ YOE Design critical AMS blocks such as PLLs, CDRs, TX drivers, RX front-ends, CTLEs, DFE, LDOs, bias generators, and ADC/DAC components for wireline transceivers.; Perform transistor-level design, simulation, and…
Python
This posting is pulled directly from Astera Labs's own Greenhouse page and applying happens on their site, not here. Posted 2026-09-28; Skip The Boards re-checks every company's board regularly and removes listings that disappear from the source.