ASIC Design Engineer (Silicon Engineering)
SpaceX · Palo Alto, CA
1+ YOE Design ASICs and/or FPGAs for Starlink projects, implementing complex SoC blocks and SoC integration tasks using Verilog/System Verilog; Optimize designs for power, performance and area; Participate in the full…
Python
This posting is pulled directly from SpaceX's own Greenhouse page and applying happens on their site, not here. Posted 2026-10-10; Skip The Boards re-checks every company's board regularly and removes listings that disappear from the source.