Tech Lead Physical Design Engineer, Power Integrity
Astera Labs · San Jose, California, United States
5+ YOE degree in Electrical Engineering, Computer Engineering, or a related field 5+ years of experience in IR drop, electromigration analysis, and power integrity sign-off for complex SoCs at advanced
Python
This posting is pulled directly from Astera Labs's own Greenhouse page and applying happens on their site, not here. Posted 2026-08-25; Skip The Boards re-checks every company's board regularly and removes listings that disappear from the source.