Sr DFT Engineer
Mythic AI · Bangalore
Knowledge of chiplet-based design limitations and their impact on physical design.; Experience in Sub-10nm designs; Familiarity and hands-on experience with Cadence toolsets .
This posting is pulled directly from Mythic AI's own Lever page and applying happens on their site, not here. Posted 2026-02-27; Skip The Boards re-checks every company's board regularly and removes listings that disappear from the source.