Senior Design Verification Engineer
Astera Labs · Tel Aviv-Yafo, Tel Aviv District, Israel
3+ YOE Verification Environment Development Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks; Develop and maintain SystemVerilog/UVM-based…
Python
This posting is pulled directly from Astera Labs's own Greenhouse page and applying happens on their site, not here. Posted 2026-08-25; Skip The Boards re-checks every company's board regularly and removes listings that disappear from the source.