ASIC/SOC DFT Engineer (Silicon Engineering)
SpaceX · Palo Alto, CA
1+ YOE Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools; Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems…
Python
This posting is pulled directly from SpaceX's own Greenhouse page and applying happens on their site, not here. Posted 2026-08-06; Skip The Boards re-checks every company's board regularly and removes listings that disappear from the source.