Principal Physical Design Engineer, STA
Astera Labs · San Jose, California, United States
10 YOE Drive timing closure from RTL through sign-off, ensuring robust timing across complex SoCs.; Develop and validate SDC constraints, including MMMC setup, to enable accurate and efficient STA analysis.; Define and manage…
Python
This posting is pulled directly from Astera Labs's own Greenhouse page and applying happens on their site, not here. Posted 2026-08-25; Skip The Boards re-checks every company's board regularly and removes listings that disappear from the source.