Principal Verification Engineer

CesiumAstro · Aliso Viejo, CA
LeverEngineeringFull-time✓ Confirmed 8 hours ago
Design and implement verification test bench infrastructure and test cases for system, chip and block level verification, using the latest tools and SystemVerilog class libraries such as OVM, UVM, and VMM.; Implement…

This posting is pulled directly from CesiumAstro's own Lever page and applying happens on their site, not here. Posted 2026-09-28; Skip The Boards re-checks every company's board regularly and removes listings that disappear from the source.

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