Formal Verification and RTL Design Software Engineer
Astera Labs · San Jose, California, United States
4-10 YOE Bachelor's, Master's degree in Electrical Engineering, Computer Science/Engineering, or equivalent experience.; 4-10 years of industry experience in software engineering, with direct exposure to RTL design, static/lint…
PythonAI/LLMRAG
This posting is pulled directly from Astera Labs's own Greenhouse page and applying happens on their site, not here. Posted 2026-10-26; Skip The Boards re-checks every company's board regularly and removes listings that disappear from the source.
More at Astera Labs
- Principal Sourcing Manager – Silicon Technologies
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- Tech Lead Engineer, Design Verification
- Principal Verification Engineer
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