Principal Logic Design Engineer - UALink IP/Subsystem
Astera Labs · Bengaluru, Karnataka, India
10-15 YOE Lead architecture and RTL development for UALink IP/subsystems.; Translate protocol and system requirements into scalable hardware architecture.; Design high-bandwidth, low-latency data paths and control logic.
This posting is pulled directly from Astera Labs's own Greenhouse page and applying happens on their site, not here. Posted 2026-09-23; Skip The Boards re-checks every company's board regularly and removes listings that disappear from the source.