DFT Design Engineering Director
Astera Labs · San Jose, California, United States
12+ YOE Define and drive the comprehensive DFT strategy for PCIe Gen3/4/5/6 switch products with 2.5D/3D packaging; Lead and mentor a team of DFT engineers across multiple product development cycles; Collaborate with design…
Machine Learning
This posting is pulled directly from Astera Labs's own Greenhouse page and applying happens on their site, not here. Posted 2026-08-25; Skip The Boards re-checks every company's board regularly and removes listings that disappear from the source.